Search - frequency divider

[Other resource] VerilogHDLshejifengpingqihe32weijishuqi

Description: 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
Platform: | Size: 159000 | Author: 少华 | Hits:

[Embeded-SCM Develop] divider3

Description: 一个3分频器。可进一步改装成实际需要的分频器使用-a divider. Can be further converted into actual use of the Frequency Divider
Platform: | Size: 29461 | Author: z9z9 | Hits:

[Other resource] dividefrequencecircuit

Description: 分频电路和包括他的数字PLL电路，能够抑制输出信号的抖动，包括第一电路模块它用输入信号作为第一参考时钟信号，并有分频器确定信号选择的分频率对输入信号进行分频-frequency divider circuit and including his figures PLL circuit, the output signal can inhibit the quiver, including the first circuit module that it is using the input signal as a first reference clock signal. Frequency Divider and determine the choice of signal frequency to input signal frequency
Platform: | Size: 1090492 | Author: 孔嘉 | Hits:

[Other resource] half_clk

Description: 用verilog编写适中分频器并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
Platform: | Size: 21859 | Author: 赖建 | Hits:

[Other resource] fdivision

Description: 用verilog编写适中分频器并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
Platform: | Size: 26364 | Author: 赖建 | Hits:

[File Operate] VHDLEXAMPLEppt

Description: 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
Platform: | Size: 527607 | Author: 刘一 | Hits:

[Other resource] fenpinqi

Description: 《分频器设计》绝对好用的EDA实验程序！已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
Platform: | Size: 1185 | Author: 潘晓峰 | Hits:

[assembly language] cpld

Description: 一个好用的整数分频电路保证你喜欢能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
Platform: | Size: 915 | Author: 王多奎 | Hits:

[Other resource] 分频器FENPIN1

Description: EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time - with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
Platform: | Size: 3131 | Author: 李培 | Hits:

[VHDL-FPGA-Verilog] fq_divider

Description: A simple program implements a frequency divider.
Platform: | Size: 743 | Author: besoyal@yahoo.gr | Hits:

[VHDL-FPGA-Verilog] 分频器FENPIN1

Description: EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
Platform: | Size: 3072 | Author: 李培 | Hits:

[VHDL-FPGA-Verilog] FPGAprogram2

Description: 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
Platform: | Size: 3072 | Author: 许嘉 | Hits:

[Embeded-SCM Develop] Hkbus16

Description: 多数位分频器.............................................可直接编译-Contents Paragraphs Page majority-Frequency Divider can be directly translated .......................
Platform: | Size: 12288 | Author: 学习 | Hits:

[VHDL-FPGA-Verilog] compDIVIDER

Description: 基于VHDL语言描述的一个分频器，根据端口值，可作为四分频，八分频等分频器使用。-based on VHDL description of a divider, according to port value, as a quarter of frequency, Frequency Divider interval such use.
Platform: | Size: 1024 | Author: djksdf | Hits:

[Other] EWB

Description: EWB做的多功能数字钟由振荡器输出稳定的高频脉冲信号作为时间基准，经分频器输出标准的秒脉冲，秒计数器满60向分计数器进位，分计数器满60向小时计数器进位，小时计数器按“12翻1”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒，可发挥部分：使闹钟具有可整点报时与定时闹钟的功能。 -EWB done by the multi-function digital clock oscillator output stable high frequency pulse signal as a time reference. Frequency Divider output by the standards of seconds pulse, aged 60 seconds to counter-counter rounding, Counter-to-60-hour counter rounding, by the Counter-hour "12 over a" law count, Counter by the decoder to display; Counting errors school circuit can be used for schools, school hours, school seconds to play : The alarm clock can be made with whole point regular alarm clock and timer functions.
Platform: | Size: 129024 | Author: zero | Hits:

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[Other resource] VerilogHDLshejifengpingqihe32weijishuqi

[Embeded-SCM Develop] divider3

[Other resource] dividefrequencecircuit

[Other resource] half_clk

[Other resource] fdivision

[File Operate] VHDLEXAMPLEppt

[Other resource] fenpinqi

[assembly language] cpld

[Other resource] 分频器FENPIN1

[VHDL-FPGA-Verilog] fq_divider

[VHDL-FPGA-Verilog] 分频器FENPIN1

[VHDL-FPGA-Verilog] FPGAprogram2

[Embeded-SCM Develop] Hkbus16

[VHDL-FPGA-Verilog] compDIVIDER

[Other] EWB

[VHDL-FPGA-Verilog] feizhenshu

[Software Engineering] VerilogHDLshejifengpingqihe32weijishuqi

[VHDL-FPGA-Verilog] my_design_frequency

[Embeded-SCM Develop] divider3

[VHDL-FPGA-Verilog] half_clk

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